A peripheral interface (such as an ATM interface) is employed in a computer system to interface communications between core logic of the computer system and an external peripheral device (such as a physical layer device or “PHY” in the case of ATM). Since the core logic uses a system clock and the peripheral device uses a peripheral clock (that is generally asynchronous to and of lower frequency than the system clock), the circuitry of the peripheral interface is separated into two clock domains, i.e., a system clock domain and a peripheral clock domain.
The system clock domain includes portions of the interface using the system clock to communicate with the core logic, and the peripheral clock domain includes portions of the interface using the peripheral clock to communicate with the peripheral device. The system clock is provided to the system clock domain internally by a system clock generator, and the peripheral clock is provided to the peripheral clock domain externally by the peripheral device.
When the system resets the peripheral device, it is desirable to be able to synchronously reset both clock domains even if the peripheral clock is not being provided at that time to the peripheral clock domain. It is also desirable to hold the reset on the peripheral clock domain until the peripheral clock is being provided once again by the peripheral device. Further, when the peripheral clock is once again being provided and the reset is released on the peripheral clock domain, it is desirable to perform that release synchronously with the peripheral clock (which is generally asynchronous to the system clock).
To circumvent the need to meet these objectives, some computer systems simply require the peripheral clock to always be provided externally by the peripheral during reset. This, however, may not always be possible or desirable. For example, a PHY may not generate the peripheral clock until it has been enabled by the core logic.
In a software approach that attempts to meet the above objectives, a status bit is set when the peripheral device has been reset. The challenge with the status bit approach is that if the peripheral clock signal is stopped, the status bit will remain in the “not reset” state for an indefinite period. Proper handling of this condition therefore requires complex software.